Example embodiments relate to apparatuses and methods for fabricating semiconductor devices. More specifically, example embodiments are directed to apparatus and method for fabricating semiconductor packages.
Semiconductor chips fabricated on a wafer are packaged to be assembled. With the recent trend toward smaller and lighter products, various types of packages have been developed to reduce packaging area and thickness.
One state-of-the-art package is a ball grid array (BGA) where balls are arranged underneath one package. The BGA is advantageous in reducing a package area and exhibits improved electric characteristics. A plastic BGA (PBGA) may use a printed circuit board (PCB) including multi-layer wirings capped to a photo solder resist (PSR) to increase data transmission speed and/or bandwidth.
FIG. 1 illustrates a conventional printed circuit board (PCB) 10 for a plastic ball grid array (PBGA). The PCB 10 may include a board body 5 and multi-layer wirings 12a and 12b disposed at a first surface 8a and a second surface 8b, respectively, of the board body 5. A chip area (not shown) and a bonding area 18 may be formed in the first surface 8a, and a buffer area 20 may be formed in the second surface 8b. Semiconductor chips 11 may be situated in the chip area, and solder balls may be disposed at the buffer area 20. The bonding area 18 may be formed to bond the semiconductor chip 11 with the first wiring 12a. The first wiring 12a and the second wiring 12b may be electrically connected by a via pattern 6 penetrating the board body 5.
The first surface 8a and second surface 8b of the PCB 10 may be covered with photo solder resist (PSR) layers 14a and 14b. The first wirings 12a and second wirings 12b may be made of copper foil to control their thicknesses, while coating thicknesses of the PSR layers 14a and 14b may be controlled less accurately.
FIG. 2 illustrates a conventional mold die for use in fabrication of semiconductor packages. The mold die may be divided into a top unit 50t and a bottom unit 50b. The top unit 50t may include a master top die 52t, a top spacer block 54t, and/or a top mold 56t. The bottom unit 50b may include a master bottom die 52b, a bottom spacer block 54b, and a bottom mold 56b. The master bottom die 52t and the master bottom die 52b may apply a clamp pressure to the top mold 56t and the bottom mold 56b, pressing a PCB 10 placed between the top and bottom molds 56t and 56b to close a cavity 60 into which a mold resin may be injected.
The top mold 56t have formed cavities 60, a cull area 68 where a molding resin 64 may be fluidized, or partially fluidized, by the force of a press arm 66, and a runner 62 along which the fluidized molding resin 64 may be allowed to flow into the cavity 60.
When the top unit 50t and the bottom unit 50b are clamped with a predetermined or given pressure, a suitable pressure may be applied to the PCB 10. However, improper clamping of the top and bottom units 50t and 51b may cause the problems shown in FIGS. 3 and 4.
As previously stated, a printed circuit board (PCB) 10 may have a thickness tolerance resulting from non-uniform coating of a photo solder resist (PSR) 65. If a PCB 10 requires a small thickness, the cavity 60 may not become fully sealed with the top surface of the PCB 10 while it is being molded by a preset clamp pressure of a mold die. For this reason, a molding resin 69 may be effused such that the resin covers a package cutting line 67. Subsequently, a package may not be separated from the PCB as shown in FIG. 3, or a cutter may be damaged as shown in FIG. 4.
In the case where the thickness of a PCB exceeds an allowable range, if a strong clamp pressure is applied to the PCB, a first wiring 12a connected to a via pattern 16 may be cut or damaged 70, as shown in FIG. 4. When the first wiring 12a is cut or damaged 70, a signal may not be transmitted to a semiconductor chip in a package. Accordingly, the package may not be used usable.
Conventionally, the spacer block 54t may be polished to control a pressure applied to a PCB. However, the thickness of a spacer block is conventionally computed by running repeated tests conducted after the fabrication of a bad package, and time is required for replacing or polishing the spacer block. Moreover, this approach cannot cope with thickness variation of all PCBs.